In electronic systems, good clock distribution is very important to the overall performance of a product. Unwanted clock skew and jitter are two phenomena that may result from poor clock distribution, thus causing problems in the design and operation of the electronic systems.
Techniques have been developed using phase lock loops (PLLs) and delay lock loops (DLLs) to successfully address these problems and reduce both to manageable levels. However, conventional solutions are not without some disadvantages. One conventional solution includes the use of a PLL and another, the use of a DLL. A typical PLL circuit of the conventional art is shown in FIG. 1, and a typical DLL circuit of the conventional art is shown in FIG. 2.
FIG. 1 shows an exemplary PLL circuit 100 of the conventional art comprising a reference clock input (Refclk) 101 to a block 110 comprising a phase-frequency detector (PFD), a charge pump (CP), and a low pass filter (LPD). In FIG. 1, the output of the phase frequency detector is input to the charge pump, which in turn drives the low pass filter. The output of the PFD/CP/LPF block 110 is a voltage (vctrl) which is input to, and controls, a voltage controlled oscillator (VCO) 120 comprising a plurality of delay stages. The output of VCO 120 is input to an on-chip delay element 130, comprising a buffer, a capacitor connected between the output of the buffer and ground, and an output of block 130. A feedback path 140 couples the output of on-chip delay element 130 to an input of PFD/CP/LPF block 110. The lower part of FIG. 1 shows the multiple delay stages (e.g., delay stages 121, 122, and 12N) in VCO 120. Importantly, the circuit 100 of FIG. 1 operates in closed loop fashion only.
In PLL 100, the phase frequency detector of PFD/CP/LPF block 110 compares the phase difference between the Refclk signal 105 and the output clock signal received via feedback path 140. Depending on the phase difference between the two signals, PFD/CP/LPF block 110 will change the vctrl voltage supplied to VCO 120, which modulates the frequency of the oscillator.
With regard to PLL 100, phase lock loops have certain advantages, e.g., PLLs can suppress skew in digital systems (e.g., clock to data out delay) and can generate multiple phases of output clocks. However, PLLs cannot operate over a wide frequency range or at a low supply voltage.
FIG. 2 shows an exemplary DLL circuit 200 of the conventional art comprising a reference clock input (Refclk) 201, a block 210 comprising a phase-frequency detector (PFD), a charge pump (CP), and a low pass filter (LPF). A voltage controlled delay element (VCDL) 220 comprises two inputs: one input is from Refclk 201; and the other is the output of the PFD/CP/LPF block 210. The output of VCDL 220 is coupled with an on-chip delay element 230 comprising a buffer, a capacitor connected between the output of the buffer and ground, and an output of block 230. A feedback path 240 couples the output of on-chip delay element 240 to an input of PFD/CP/LPF 210. The lower part of FIG. 1 shows the multiple delay stages (e.g., delay stages 221, 222, and 22N) in VCDL 220. As shown in FIG. 2, VCDL is a straight delay chain (e.g., open loop) and is not self-oscillatory like VCO 120 of FIG. 1.
In DLL circuit 200, the phase frequency detector of PFD/CP/LPF block 210 compares the phase difference between the Refclk signal 201 and the output clock signal received via feedback path 240. Depending on the phase difference between the two signals, PFD/CP/LPF block 210 will change the vctrl voltage supplied to VCDL 120, which modulates delay time through the delay stages 221–22N.
One DLL alone can either suppress skew in digital systems (e.g., clock to data out delay) or generate multiple phases for a limited frequency range. To achieve both of these, two DLLs must typically be used in series (in cascade), one for skew suppression and one for clock phase generation. However, when using more than one DLL in cascade, unwanted deterioration in jitter performance is exhibited as the errors introduced by each circuit are additive. Jitter may be defined as the uncertainty in the placement of the leading and trailing edges of the clock signal. Factors affecting jitter performance include process voltage, temperature, and switching condition noise. In other words, greater uncertainty in the placement of the clock edges is introduced when multiple DLLs are used achieve skew suppression and generate multiple clock phases.